This application claims the priority of Korean Patent Application No. 2002-44677, filed Jul. 29, 2002 in the Korean Intellectual Property Office (KIPO), which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to a memory controller for use in a computer system, and more particularly, to a memory controller which increases the bandwidth of a bus in a multi-bus system, a data transmission method using the same, and a computer system including the memory controller.
2. Description of the Related Art
In general, a computer system consists of three primary subsystems: memory, at least one central processing unit (CPUs), and input/output (I/O) devices.
To satisfy the various needs of users, computers have been developed to be connected to various types of subsystems via a number of communication protocols, including peripheral component interconnect (PCI), Ethernet, or a universal asynchronous receiver/transceiver (UART).
In a computer system, interfaces are required to conduct communication between various types of subsystems. For instance, communication between the memory and the CPU, or between the CPU and the I/O devices may be conducted via a bus.
A bus is a communication line in which several wires are bound with each other in parallel and shared by several subsystems. The maximum bus speed is limited primarily by physical factors such as the physical length of a bus and capacitive loading of the bus.
According to computer architecture theory, a CPU and memory are required to adopt Von Neumann Architecture, i.e., a stored program method. In order to increase the performance of a computer system, both the performance of the CPU and memory should be increased.
However, while CPUs have been developed to increase operating speed, memory, such as dynamic random access memory (DRAM), has been developed to increase memory capacity, while not keeping pace CPU advances in terms of operating speed. Thus, in current systems, the operating speed of memory is remarkably lower than that of CPUs.
Operating speeds of subsystems, such as PCI, Ethernet, and UART, used in computer systems, are also lower than that of the CPU.
Therefore, the performance of a computer system or memory system is evaluated by memory latency or memory access, and memory bandwidth. That is, the smaller the memory latency and the larger the memory bandwidth, the better the performance of the computer system.
To improve the performance of a computer system, the bus bandwidth between the memory and the CPU, i.e., the I/O ports of memory, is increased. This method, however, increases the size of a DRAM chip and causes cross-talk noise between the I/O ports, thereby lowering the operating speed of the computer system.
When the performance of a subsystem such as PCI, Ethernet, or UART, is not developed as rapidly as the development of the performance of a CPU, such a subsystem must be redeveloped to design a computer system which does not restrain the operating speed of the CPU.
For instance, if the CPU is 2N-bit device, and PCI, Ethernet, or UART is an N-bit device (N is 32), the PCI, Ethernet, or UART must be redesigned to be 2N-bit devices in order to design a true 2N-bit computer system.